FIG. 1 is a circuit diagram of a semiconductor device of the background art, showing an example of the structure of a semiconductor memory, particularly of its output buffer circuit portion. Referring to FIG. 1, a memory cell array MCA has a plurality of memory cells MC each capable of storing a data. An address Ai selects one memory cell MC. A data in the selected memory cell MC is outputted as complementary data and inputted via data lines D and D to an output buffer OB. Specifically the complementary data is supplied via output gate circuits OG1 and OG2 to output transistors Tr1 and Tr2. An on/off of the output gate circuits OG1 and OG2 is controlled by an output enable signal OE. An equalizing transistor Tr0 is connected between the data lines D and D. This transistor Tr0 equalizes the data lines D and D upon reception of an equalizing signal .phi..sub.Eq temporarily inputted at the time of address transition. The transistors Tr1 and Tr2 operate in a complementary manner. An output signal from the interconnection between the transistors Tr1 and Tr2 is transferred to an I/O pin.
The operation of the semiconductor device constructed as above will be described below.
Complementary output signals from a selected memory cell MC are outputted onto the data lines D and D. As an address transits and a different memory cell is selected, output signals from the memory cell cause the data level of the data lines D and D to change. In order to allow high speed access to a memory cell, the data lines D and D are equalized. The transistor Tr0 is used for this purpose. When the equalizing signal .phi..sub.Eq is applied to the transistor Tr0, the data lines D and D are equalized to an intermediate level between V.sub.CC and V.sub.SS. In this case, in order to prevent a through current from flowing from the power source V.sub.CC to the power source V.sub.SS via the output transistors Tr1 and Tr2, the output gate circuits OG1 and OG2 are both closed by the output enable signal OE so that the output transistors Tr1 and Tr2 are turned off at the same time. The I/O pin therefore becomes high impedance. Next, after the data lines D and D are fully equalized and the output data from the selected memory cell is established, the output gate circuits OG1 and OG2 are opened by the output enable signal OE. Then, the data on the data lines D and D is supplied to the gates of the transistors Tr1 and Tr2 via the output gate circuits OG1 and OG2. As a result, one of the transistors Tr1 and Tr2 turns on and the other turns off, so that the data is outputted from the memory circuit to the I/O pin.
During such operations described above, a circuit for detecting an address transition of the memory circuit sometimes operates erroneously because of fluctuations of the power supply voltage. For example, there occurs a case that the equalizing signal .phi..sub.Eq is outputted erroneously for a very short time. As a result, the transistor Tr0 turns on erroneously and the data lines D and D are equalized. This erroneous equalization causes a temporary unstable state of the potentials at the data lines D and D, i.e., the input voltages to the two gates of the transistors Tr1 and Tr2. In other words, if the erroneous equalization occurs when the output data on the data lines D and D is changing in accordance with the outputs from a newly selected memory cell, the establishment of the output data is temporarily stopped. Data output from the output transistors Tr1 and Tr2 to the I/O pin is therefore delayed, hindering high speed access.
A semiconductor device shown in FIG. 2 has been proposed for solving the above problem. As shown in FIG. 2, latch circuits L1 and L2 are provided at the gate side of the output transistors Tr1 and Tr2. The latch circuits L1 and L2 prevent the gate inputs to the output transistors Tr1 and Tr2 from entering an unstable state by noise which operates in the same manner as the equalizing signal .phi..sub.Eq. Particularly, the latch circuits L1 and L2 hold the gate input state so that a data output delay can be avoided. Furthermore, the output buffers connected to the output transistors Tr1 and Tr2 are constructed of tri-state buffers. With such an arrangement, while the data lines D and D are equalized by an output from a buffer control circuit BC, the buffer control circuit BC outputs signals for controlling the output buffer circuits B1 and B2 such that the outputs supplied to the gates of the output transistors Tr1 and Tr2 from the circuits B1 and B2 are made high impedance. In this case, if the output enable signal OE is not inputted to the buffer control circuit BC, it is apparent that the output buffer circuits B1 and B2 turn off the gates of the output transistors Tr1 and Tr2. However, on the other hand, if the output enable signal OE is inputted to the buffer control circuit BC, the output buffer circuits B1 and B2 allow the levels per se at the data lines D and D to be supplied to the gates of the output transistors Tr1 and Tr2. In this condition, if the equalizing signal .phi..sub.Eq is inputted to the buffer control circuit BC, outputting the output enable signal OE is inhibited so that the outputs of the output buffer circuits B1 and B2 are made high impedance. Consequently, the gate potentials of the output transistors Tr1 and Tr2 are held at the data in the latch circuits L1 and L2.
With the circuit arrangement shown in FIG. 2, even if a noise signal operating as the equalizing signal .phi..sub.Eq is inputted, the outputs of the output transistors are not prevented from being established, thereby allowing a rapid establishment of output data at the I/O pin.
The operation of the two semiconductor devices shown in FIGS. 1 and 2 will further be detailed below.
The circuit operation of the semiconductor device shown in FIG. 1 for reading a "0" level to be changed from a "1" level from a memory cell MC will be described with reference to the timing charts shown in FIGS. 3A to 3F. FIG. 3A shows a change in potential of the equalizing signal .phi..sub.Eq with time, FIG. 3B shows a change in the potential of the data lines D and D with time, FIG. 3C shows a change in gate potential of the output transistors Tr1 and Tr2 with time, FIG. 3D shows a change in potential at the I/O pin connected to the interconnection between the output transistors Tr1 and Tr2 with time, FIG. 3E shows a change in V.sub.CCin and V.sub.SSin within the chip of the semiconductor circuit, and FIG. 3F shows a change in potential of the external input to an address buffer from the outside of the chip with time, relative to the reference potential of V.sub.SSin within the semiconductor circuit.
As shown in FIG. 3F, consider the case where a voltage inputted to an address buffer (not shown) changes from a lower voltage to a higher voltage than a threshold value V.sub.thADB of the buffer circuit. When the buffer circuit operates, the equalizing signal .phi..sub.Eq temporarily takes a "0" level at time t1 so that the data lines D and D are equalized to take an intermediate level. Next, the output gate circuits OG1 and OG2 detect the intermediate level as V.sub.IH and cause the gate potentials V.sub.GTr1 and V.sub.GTr2 of the output transistors Tr1 and Tr2 to take a "0" level. Both the output transistors Tr1 and Tr2 therefore turn off. Next at time t2 the equalization terminates and a newly read-out data reaches so that the data line D changes from a "1" level to "0" level whereas the data line D changes from a "0" level to "1" level. As a result, the gate level V.sub.GTr2 of the output transistor Tr2 takes a "1" level and is turned on. The transistor Tr1 remains in an off-state. Therefore, a large current flows via the transistor Tr2 from the I/O pin to the inside of the semiconductor circuit chip, resulting in a temporal rise of the power supply voltages V.sub.CCin and V.sub.SSin within the chip by .DELTA.V. Accordingly, the potential V.sub.in of the input signal to the address buffer has a potential difference from the voltage V.sub.SSin within the chip, i.e., becomes lower than the latter by .DELTA.V.
If the input potential V.sub.in has at first a potential higher than the address buffer circuit threshold value V.sub.thADB by the amount smaller than .DELTA.V, the address buffer falsely and temporarily considers the input potential not as the real V.sub.IH but as the V.sub.IL, resulting in an erroneous operation. Therefore, the equalizing signal .phi..sub.Eq again takes a "0" level at time t3 which causes the data lines D and D to take the intermediate level. As a result, in the similar manner as above, the gate potentials inputted to the output transistors Tr1 and Tr2 change from a "1" level to "0" level so that both the transistors Tr1 and Tr2 turn off, temporarily intercepting electric discharge from the I/O pin to the inside of the chip. The electric discharge resumes at time t4. From the above reason, data reading speed delays.
Next, the circuit operation of the semiconductor device shown in FIG. 1 for reading a "1" level to be changed from a "0" level from a memory cell MC will be described with reference to the timing charts shown in FIGS. 4A to 4F. FIG. 4A shows a change in potential of the equalizing signal .phi..sub.Eq with time, FIG. 4B shows a change in potential of the data lines D and D with time, FIG. 4C shows a change in gate potential of the output transistors Tr1 and Tr2 with time, FIG. 4D shows a change in potential at the I/O pin connected to the interconnection between the output transistors Tr1 and Tr2 with time, FIG. 4E shows a change in V.sub.CCin and V.sub.SSin within the chip of the semiconductor circuit, and FIG. 4F shows a change in potential of the external input to an address buffer from the outside of the chip with time, relative to the reference potential of V.sub.SSin within the semiconductor circuit.
As shown in FIG. 4F, consider the case where a voltage inputted to an address buffer (not shown) changes from a higher voltage to a lower voltage than a threshold value V.sub.thADB of the buffer circuit. When the buffer circuit operates, the equalizing signal .phi..sub.Eq temporarily takes a "0" level at time t1 so that the data lines D and D are equalized to take an intermediate level. Next, the output gate circuits OG1 and OG2 detect the intermediate level as V.sub.IH and cause the gate potentials V.sub.GTr1 and V.sub.GTr2 of the output transistors Tr1 and Tr2 to take a "0" level. Both the output transistors Tr1 and Tr2 therefore turn off. Next at time t2 the equalization terminates and a newly read-out data reaches so that the data line D changes from a "0" level to "1" level whereas the data line D changes from a "1" level to "0" level. As a result, the gate level V.sub.GTr1 of the output transistor Tr1 takes a "1" level and is turned on. The transistor Tr2 remains in an off-state. Therefore, a large current flows via the transistor Tr1 from the I/O pin to the inside of the semiconductor circuit chip, resulting in a temporal fall of the power supply voltages V.sub.CCin and V.sub.SSin within the chip by .DELTA.V. Accordingly, the potential V.sub.in of the input signal to the address buffer has a potential difference from the voltage V.sub.SSin within the chip, i.e., becomes higher than the latter by .DELTA.V.
If the input potential V.sub.in has at first a potential lower than the address buffer circuit threshold value V.sub.thADB by the amount smaller than .DELTA.V, the address buffer falsely and temporarily considers the input potential not as the real V.sub.IL but as the V.sub.IH, resulting in an erroneous operation. Therefore, the equalizing signal .phi..sub.Eq again takes the "0" level at time t3 which causes the data lines D and D to take the intermediate level. As a result, in the similar manner as above, the gate potentials inputted to the output transistors Tr1 and Tr2 change from a "1" level to the "0" level so that both the transistors Tr1 and Tr2 turn off, temporarily intercepting electric charge from the inside of the chip to the I/O pin via the transistor Tr1. The electric charge resumes at time t4. For the above reason, the data reading speed is reduced.
The circuit shown in FIG. 2 has been proposed to solve the above problems. With the circuit shown in FIG. 2, even if noises operating in the same manner as the equalizing signal .phi..sub.Eq are generated at the time of address transition, the gate potentials of the output transistors Tr1 and Tr2 are being held by the latch circuit L1 and L2, preventing a delay in circuit operations.
Next, the circuit operation of the semiconductor device shown in FIG. 2 for reading the "0" level to be changed from the "1" level from a memory cell MC will be be described with reference to the timing charts shown in FIGS. 5A to 5F. FIG. 5A shows a change in potential of the equalizing signal .phi..sub.Eq with time, FIG. 5B shows a change in potential of the data lines D and D with time, FIG. 5C shows a change in gate potential of the output transistors Tr1 and Tr2 with time, FIG. 5D shows a change in potential at the I/O pin connected to the interconnection between the output transistors Tr1 and Tr2 with time, FIG. 5E shows a change in V.sub.CCin and V.sub.SSin within the chip of the semiconductor circuit, and FIG. 5F shows a change in potential of the external input to an address buffer from the outside of the chip with time, relative to the reference potential of V.sub.SSin within the semiconductor circuit.
As shown in FIG. 5F, consider the case where a voltage inputted to an address buffer (not shown) changes from a lower voltage to a voltage higher than a threshold value V.sub.thADB of the buffer circuit. When the buffer circuit operates, the equalizing signal .phi..sub.Eq temporarily takes the "0" level at time t1 so that a p-channel transistor Tr0 turns on to equalize the data lines D and D which in turn take an intermediate level. While the equalizing signal .phi..sub.Eq takes the "0" level, the output buffer circuits B1 and B2 which control the gate potentials V.sub.GTr1 and V.sub.GTr2 of the output transistors, enter a high impedance state. As a result, the latch circuits L1 and L2 hold the previous gate potentials. Next, the equalization terminates at time t2 and the equalizing signal takes .phi..sub.Eq the "1" level. Therefore, the output buffer circuits B1 and B2 enter a low impedance state. The output buffer circuits B1 and B2 detect the intermediate level as V.sub.IH and cause the gate potentials V.sub.GTr1 and V.sub.GTr2 of the output transistors Tr1 and Tr2 to change from the "1" level to the "0" level. Next, a newly read-out data reaches the data lines D and D. Namely, the data line D changes from the "1" level to the "0" level whereas the data line D changes from the "0" level to "1" level. As a result, the gate levels V.sub.GTr1 and V.sub.GTr2 of the output transistors Tr1 and Tr2 take the "0" level and the "1" level, respectively, turning off the output transistor Tr1 and turning on the output transistor Tr2. Therefore, a large current flows from the I/O pin to the inside of the semiconductor circuit chip, resulting in a temporary rise of the power supply voltages V.sub.CCin and V.sub.SSin within the chip by .DELTA.V. Accordingly, the potential V.sub.in of the input signal to the address buffer has a potential difference from the voltage V.sub.SSin within the chip, i.e., becomes higher than the latter by .DELTA.V, when compared with the case before the large current flows from the I/O pin to the inside of the semiconductor circuit chip.
If the input potential V.sub.in has at first a potential higher than the address buffer circuit threshold value V.sub.thADB by the amount smaller than .DELTA.V, the address buffer falsely and temporarily considers the input potential as V.sub.IH, resulting in an erroneous operation. Therefore, the equalizing signal .phi..sub.Eq again takes the "0" level at time t3 which causes the data lines D and D to take the intermediate level. In this case however, since the output buffer circuits B1 and B2 are in the high impedance state, the gate potentials of the output transistors Tr1 and Tr2 are being held at the "0" level and "1" level, respectively, by the latch circuits L1 and L2.
The output buffer circuits B1 and B2 however enter a low impedance state when the equalizing signal .phi..sub.Eq takes the "1" level at time t4. Therefore, the output buffer circuit B2 detects the intermediate level at the data line as V.sub.IH to that the gate potential of the output transistor Tr2 take the "0" level. As a result, during the period from when a newly read-out data again reaches the data lines D and D to when the gate potential of the output transistor Tr2 again takes the "1" level, electric discharge from the I/O pin to the inside of the chip is intercepted, resulting in a delay in the data reading speed.
Next, the circuit operation of the semiconductor device shown in FIG. 2 for reading the "1" level to be changed from the "0" level from a memory cell MC of the memory cell array MCA will be described with reference to the timing charts shown in FIGS. 6A to 6F. FIG. 6A shows a change in potential of the equalizing signal .phi..sub.Eq with time, FIG. 6B shows a change in potential of the data lines D and D with time, FIG. 6C shows a change in gate potential of the output transistors Tr1 and Tr2 with time, FIG. 6D shows a change in potential at the I/O pin connected to the interconnection between the output transistors Tr1 and Tr2 with time, FIG. 6E shows a change in V.sub.CCin and V.sub.SSin within the chip of the semiconductor circuit, and FIG. 6F shows a change in potential of the external input to an address buffer from the outside of the chip with time, relative to the reference potential of V.sub.SSin within the semiconductor circuit.
As shown in FIG. 6F, consider the case where a voltage inputted to an address buffer (not shown) changes from a higher voltage to a lower voltage than a threshold value V.sub.thADB of the buffer circuit. When the buffer circuit operates, the equalizing signal .phi..sub.Eq temporarily takes a "0" level at time t1 so that the p-channel transistor Tr0 turns on to equalize the data lines D and D which in turn take an intermediate level. While the equalizing signal .phi..sub.Eq takes the "0" level, the output buffer circuits B1 and B2 which control the gate potentials V.sub.GTr1 and V.sub.GTr2 of the output transistors, enter a high impedance state. As a result, the latch circuits L1 and L2 hold the previous gate potentials. Next, the equalization terminates at time t2 and the equalizing signal .phi..sub.Eq takes the "1" level. Therefore, the output buffer circuits B1 and B2 enter a low impedance state. The output buffer circuits B1 and B2 detect the intermediate level as V.sub.IH and cause the gate potentials V.sub.GTr1 and V.sub.GTr2 of the output transistors Tr1 and Tr2 to change from the "1" level to a "0" level. Next, a newly read-out data reaches the data lines D and D. Namely, the data line D changes from the "0" level to the "1" level whereas the data line D changes from the "1" level to the "0" level. As a result, the gate levels V.sub.GTr1 and V.sub.GTr2 of the output transistors Tr1 and Tr2 take the "1" level and the "0" level, respectively, turning on the output transistor Tr1. Therefore, a large current flows from the inside of the semiconductor circuit chip to the I/O pin via the output transistor Tr1, resulting in a temporary fall of the power supply voltages V.sub.CCin and V.sub.SSin within the chip by .DELTA.V. Accordingly, the potential V.sub.in of the input signal to the address buffer has a potential difference from the voltage V.sub.SSin within the chip, i.e., becomes higher than the latter by .DELTA.V, as compared with the case before the large current flows from the inside of the chip to the I/O pin.
If the input potential V.sub.in has at first a potential lower than the address buffer circuit threshold value V.sub.thADB by the amount smaller than .DELTA.V, the address buffer falsely and temporarily considers the input potential as V.sub.IH, resulting in an erroneous operation. Therefore, the equalizing signal .phi..sub.Eq again takes a "0" level at time t3 which causes the data lines D and D to take the intermediate level. In this case however, since the output buffer circuits B1 and B2 are in the high impedance state, the gate potentials V.sub.GTr1 and V.sub.GTr2 of the output transistors Tr1 and Tr2 are being held at the "1" level and the "0" level, respectively, by the latch circuits L1 and L2.
The output buffer circuits B1 and B2 however enter a low impedance state when the equalizing signal .phi..sub.Eq takes the "1" level at time t4. Therefore, the output buffer circuit B1 detects the intermediate level at the data line D as V.sub.IH so that the gate potential V.sub.GTr1 of the output transistor Tr1 take the "0" level. As a result, during the period from when a newly read-out data again reaches the data lines D and D to when the gate potential V.sub.GTr1 of the output transistor Tr1 again takes the "1" level, electric charge from the inside of the chip to the I/O pin is intercepted, resulting in a delay of data reading speed.
Semiconductor devices of the background art have been heretofore constructed as described above. If there is not a sufficient potential difference between the potential of an external input signal such as an address signal and a threshold value of a buffer circuit for receiving such an external input signal, data reading speed delays because of variations of the level of the power supply voltage or ground voltage within the semiconductor circuit chip, raising an obstacle against high speed access to a memory circuit.